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Generate NetList (gnl) is a research tool that allows the
generation of logic level synthetic benchmark circuits (netlists). The
circuit generation is based on a bottom-up recursive clustering of
blocks or modules (subcircuits) into larger modules, which finally
results in the complete circuit. The blocks or modules are combined by
connecting net terminals and thus creating the nets between the
blocks. This net generation process is done according to Rent's
rule. A mechanism is provided to prevent the generation of
combinational loops, and the maximum path length during net generation
can be controlled. Details on the algorithm can be found in various papers.
Copyright (c) 1998-2002 Peter Verplaetse, Dirk Stroobandt
Affiliation: Ghent University, Department of Electronics and Information Systems, St.-Pietersnieuwstraat 41, 9000 Gent, Belgium
Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR
THE USE OR OTHER DEALINGS IN THE SOFTWARE.
The program is entirely written in C++. Part of the C++ code (the command line parsing routines) are automatically generated by a Perl script. The code has been tested on Linux, HP-UX and SunOs. The compiler we used is gcc-2.96. It will probably work fine on other platforms as well, but this has not been tested yet. If you do, please let us know.
The source files argread.cc and argread.h are generated from argread.arf with
the tool arf2cc.
The program has the following command line interface:
gnl [options] <XX.gnl>
The input file <XX.gnl> is the circuit specification file for gnl. The format
of this file will be discussed in the following section. The command line
options will be discussed in the next section. It might be useful to have a
look at the examples that come with the distribution as well.
The gnl specification file consists of one or multiple library sections, possible module sections and finally one circuit section. Each section starts with a header line between square brackets. Comments can be included in the gnl file, and must be preceded by the comment prefix character '#'.
The library section looks like this:
[library] name=lib latch=dff 1 1 latch=dffq 1 2 gate=inv 1 1 gate=and2 2 1 gate=nand3 3 1 gate=or4 4 1 gate=xor2 2 1
The library name must be specified, and is followed by one or multiple lines of the form
{gate|latch} = <cell name> <number of inputs> <number of outputs>
The keyword 'gate' is used for combinational blocks. Sequential blocks are marked by the keyword 'latch'. The cell name should be unique for each library. The number of inputs and number of outputs must be a non-negative number.
The circuit or module section looks like this:
[circuit] name=large libraries=lib distribution=500 500 3000 2000 1500 1000 500 size=30 p=0.7 q=0.6 size=3000 p=0.55 q=0.5 size=9000 I=350 O=150
Circuits start with the header [circuit], whereas modules start with the header [module]. The circuit name is optional; in case no name is specified, the default 'top' is used. Module names are not optional, since they act as library names for parent modules.
The libraries are a list of used libraries or child modules. Hence, a module appears as a library that contains a single (macro-)cell. The distribution is a list of numbers that corresponds to the number of instances of each cell in the libraries. Multiple distribution lines can be specified, and it is advised to use a single distribution entry for each library or child module.
The different Rent regions are specified by the size keyword (which represents the upper bound for that region), and optionally followed by the following entries: (note: T is the number of terminals, thus T=I+O with I being the number of inputs and O being the number of outputs. The parameter g is the output fraction, i.e. g=O/T=O/(I+O))
| meanT | = | <mean T at end of region> | |
| p | = | <Rent exponent, default: 0.6> | |
| sigmaT | = | <standard deviation for T at end of region> | |
| q | = | <exponent for standard deviation for T, default: p-0.1> | |
| meanG | = | <mean g at end of region, default: 0.3> | |
| sigmaG | = | <standard deviation for g for the complete region, default: 0.15> |
It is not allowed to specify both p and meanT, or both q and sigmaT, since one can be calculated from the other. At least one Rent region must be specified: the end region, for which the region bound equals the total circuit size. This total circuit size must correspond to the size as specified by the library distribution. For this end region, the number of primary inputs and/or outputs can be specified as
| I | = | <number of primary inputs> | |
| O | = | <number of primary outputs> |
If both are specified, this supersedes meanT and meanG. Optionally, a region with boundary size=1 can be specified as well. For this special start region, no p or q value can be specified. It is only useful for multi-level netlist generation, since in that case the calculation of the start region parameters from the library distribution will give bogus results.
This version of gnl provides enhanced control of the maximum path length and the path length distribution. The following method is being used:
By default, the maximum path length is set to 40 blocks, and the cutoff size is set to 70 percent.
Other features are added to increase control over the Rent behavior of the generated circuits. Both options are enabled by default:
| -f <file> | Options & arguments file |
| Use this option to specify a file that contains further command line options and arguments. | |
| -v | Verbose mode on |
| Write log to stdout as well. | |
| -d <level> | Debug mode on |
| For debug purposes. A gnl.debug file will be written. See debug.h for details on debug levels. | |
| -log <file> | Log filename |
| Concise logging information is written to the default log file gnl.log. If the environment variable PVLOGS is set and points to an existing directory, the log file is written to that directory. A different log file name can be specified with the -log option. |
| -sp | Show progress A decrementing counter is shown, and represents the number of modules that need to be combined. |
| -eP <%error> | Warn if error on number of pins too big [20] |
| Show a warning if the final number of pins of a circuit or module is off by a certain amount. | |
| -eg <%error> | Warn if error on final output fraction too big [20] |
| Show a warning if the final output fraction of a circuit or module is off by a certain amount. | |
| -nw | Don't show warnings |
| Don't warn if the number of pins or output fraction deviates too much. |
| -w <formats> | Output formats (hnl,netD,nets,info,plot,rtd,dat) [hnl] |
Write the circuit netlist or details to the following output
formats (multiple formats can be specified):
| |
| -wm <formats> | Output formats for internal macrocells |
| Write the netlist or details for the modules in case of multilevel netlist generation. | |
| -wa | Write output for all modules (-wm identical to -w) |
| The -wm option is ignored, and the -w option is also used for the internal modules that are generated during multilevel netlist generation. |
| -mpl | Maximum path length [40] |
| Absolute maximum path length | |
| -plc | Path length cut-off percentage [70] |
| Maximum module size (on a logarithmic scale) to scale path lengths | |
| -dsd | Delay shape distribution [ 0 .. 0 1 ] |
| Distribution from which the maximum delays are sampled (scaled to the absolute maximum path length). When no distribution is specified, all maximum path lenths are set to the absolute maximum path length | |
| -msb | Minimum number of blocks for sequential combination [0] |
| Minimum module size to allow a combination with a sequential block | |
| -mipl | Minimum path length [0] |
| Minimum path length to allow a net combination | |
| -ap | Allow long paths |
| Deactivates path length control. | |
| -al | Allow combinational loops (this implies -ap) |
| Deactivates combinational loop prevention and path length control. |
| -nlc | Do not allow local connections |
| Do not allows connections from modules to themselves | |
| -lcc | Local connection cut-off percentage [60] |
| Minimum module size (on a logarithmic scale) to allow local connections. | |
| -nfi | Do not allow flop insertion |
| No flip flop insertion (equivalent to -fip 0) | |
| -fic | Flop insertion cut-off percentage [70] |
| Minimum module size (on a logarithmic scale) to allow flop insertion. | |
| -fip | Flop insertion cut-off probability [0.1] |
| Probability that a flip flop is inserted when no connection is allowed without exceeding the maximum path length | |
| -dbf <factor> | Distribution correction bucket factor [1.3] |
| The terminal distribution is corrected using a feedback mechanism. The actual distribution mean is calculated using buckets with a certain width, which appears as a factor in the logarithmic domain. Use this option to change the default bucket factor. | |
| -dct <num> | Distribution correction threshold [2] |
| Terminal count distribution correction is applied as soon as the number of modules in the bucket exceeds this value. | |
| -dtc <fraction> | Distribution mean T correction factor [0.2] |
| The target mean terminal count is corrected by this fraction of the error between the target and actual mean value. | |
| -dgc <error> | Distribution mean G correction factor [0.01] |
| The target mean output fraction is corrected by this fraction of the error between the target and actual mean value. | |
| -mstg <fraction> | Minimum sigma T factor [2.0] |
| A cell can not be selected for combination with a module unless the number of terminals is less than MeanT+<factor>*SigmaT that corresponds to the number of blocks of the other module. |
| -cms | Combine modules according to module size |
| By default, the modules are combined in a random order. This option forces combination of the smaller modules first. This results in a more regular and balanced partitioning tree. | |
| -mini <min in> | Minimum number of intermediate input pins [1] |
| Minimum number of intermediate input pins. | |
| -mino <min out> | Minimum number of intermediate output pins [1] |
| Minimum number of intermediate output pins. | |
| -seed <seed> | Initial seed [1] |
| Initial seed for random number generation. |