Kristof Beyls' home page

Contact info
Links
Publications

Contact info

Kristof Beyls
Sint-Pietersnieuwstraat 41
9000 Gent
Belgium

e-mail: Kristof.Beyls at elis.UGent.be
Tel. +32 9 2649528

links

• More information about the reuse distance can be found on the Reuse Distance Research Wiki.
• The RDVIS (Reuse Distance Visualizer) has been released publically. It shows the source code patterns in your code that lead to low temporal data locality. Based on the visualized patterns, program transformations to improve temporal locality and reduce the number of data cache misses can often be found within minutes.
• The SLO-tool (Suggestions for Locality Optimzations) has been released publically. It analyzes the code that is executed between data reuses, and based on that analysis it suggests code refactorings to improve the programs temporal data locality.
• Also visit the Parallel Programming Tools website! It contains further information about our research.

Publications

Ph.D. thesis

1. Beyls, K. Software Methods to Improve Data Locality and Cache Behavior. Doctoraatsproefschrift Faculteit Toegepaste Wetenschappen, Universiteit Gent. Promotor: D'Hollander, E. 2004. [BibTeX][PDF][PPT]

Journal papers

1. Beyls, K.; D'Hollander, E. Refactoring for Data Locality. IEEE Computer. Vol. 42 (2). 2009. pp. 62-71 [BibTeX][Abstract][PDF]
2. Beyls, K.; D'Hollander, E. Refactoring Intermediately Executed Code to Reduce Cache Capacity Misses. The Journal of Instruction-Level Parallelism. Vol. 10. 2008. pp. 1-9 (Digitaal) [BibTeX][Abstract][PDF]
3. Devos, H.; Beyls, K.; Christiaens, M.; Van Campenhout, J.; D'Hollander, E.; Stroobandt, D. Finding and Applying Loop Transformations for Generating Optimized FPGA Implementations. Transactions on High Performance Embedded Architectures and Compilers I. Springer-Verlag Berlin Heidelberg. Lecture Notes in Computer Science. Vol. 4050 ( ). 2007. pp. 159--178 [BibTeX][Abstract][PDF]
4. Verdoolaege, S.; Seghir, R.; Beyls, K.; Loechner, V.; Bruynooghe, M. Counting Integer Points in Parametric Polytopes Using Barvinok\`s Rational Functions. Algorithmica. Springer New York. Vol. 48. 2007. pp. 37-66 [BibTeX][Abstract][PDF]
5. Beyls, K.; D'Hollander, E. Generating Cache Hints for Improved Program Efficiency. Journal of Systems Architecture. Elsevier. Vol. 51 (4). 2005. pp. 223-250 [BibTeX][Abstract][PDF]
6. Yu, Y.; Beyls, K.; D'Hollander, E. Visualizing the impact of the cache on program execution. Communication and Cognition - Artificial Intelligence. communication and cognition. Vol. 19 (3-4). 2002. pp. 151-172 [BibTeX][Abstract]
7. Beyls, K.; D'Hollander, E. Compiler Generated Multithreading to Alleviate Memory Latency. Journal of Universal Computer Science. Springer Pub. Co.. Vol. 6 (10). 2000. pp. 968-993 [BibTeX][PDF]

Conference papers

1. Diet, F.; D'Hollander, E.; Beyls, K.; Devos, H. Embedding smart buffers for window operations in a stream-oriented C-to-VHDL compiler.. Proceedings of the 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008. IEEE. 2008. pp. 142-147 [BibTeX]
2. Devos, H.; Beyls, K.; Christiaens, M.; Van Campenhout, J.; Stroobandt, D. From Loop Transformation to Hardware Generation. Proceedings of the 17th ProRISC Workshop. 2006. pp. 249-255 [BibTeX][Abstract][PDF][PDF]
3. Beyls, K.; D'Hollander, E. Discovery of Locality-Improving Refactorings by Reuse Path Analysis. Proceedings of the 2nd International Conference on High Performance Computing and Communications (HPCC). Springer. Lecture Notes in Computer Science. Vol. 4208. 2006. pp. 220--229 [BibTeX][Abstract][PDF][PPT]
4. Beyls, K.; D'Hollander, E. Intermediately Executed Code is the Key to Find Refactorings that Improve Temporal Data Locality. Proceedings of the 3rd conference on Computing frontiers. ACM. 2006. pp. 373-382 [BibTeX][Abstract][PDF][PPT]
5. Beyls, K.; D'Hollander, E.; Vandeputte, F. RDVIS: A Tool that Visualizes the Causes of Low Locality and Hints Program Optimizations. Computational Science -- ICCS 2005, 5th International Conference. Springer. Lecture Notes in Computer Science. Vol. 3515. 2005. pp. 166-173 [BibTeX][Abstract][PDF][PPT]
6. Verdoolaege, S.; Beyls, K.; Bruynooghe, M.; Catthoor, F. Experiences with Enumeration of Integer Projections of Parametric Polytopes. Compiler Construction: 14th International Conference. Springer. Lecture Notes in Computer Science. Vol. 3443. 2005. pp. 91-105 [BibTeX][Abstract][PDF][PPT]
7. Verdoolaege, S.; Seghir, R.; Beyls, K.; Loechner, V.; Bruynooghe, M. Analytical Computation of Ehrhart Polynomials: Enabling more Compiler Analyses and Optimizations. Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems (CASES). ACM. 2004. pp. 248-258 [BibTeX][Abstract][PDF][PDF]
8. Yu, Y.; Beyls, K.; D'Hollander, E. Performance Visualizations using XML representations. Proceedings of the eigth international conference on information visualization. IEEE. 2004. pp. 795-800 [BibTeX][PDF][PPT]
9. Beyls, K.; D'Hollander, E. Platform-Independent Cache Optimization by Pinpointing Low-Locality Reuse. Computational Science - ICCS 2004: 4th International Conference, Proceedings, Part III. Springer-Verlag Heidelberg. Lecture Notes in Computer Science. Vol. 3038. 2004. pp. 448-455 [BibTeX][Abstract][PDF][PPT]
10. Verdoolaege, S.; Beyls, K.; Bruynooghe, M.; Seghir, R.; Loechner, V. Analytical Computation of Ehrhart Polynomials and its Applications for Embedded Systems. 2nd Workshop on Optimizations for DSP and Embedded Systems. 2004. [BibTeX][PDF]
11. Beyls, K.; D'Hollander, E. Compile-Time Cache Hint Generationfor EPIC Architectures. Proceedings of the 2nd workshop on Explicitly Parallel Instruction Computing Architectures and Compiler Techniques. 2002. [BibTeX][PDF]
12. Beyls, K.; D'Hollander, E.; Yu, Y. Visualization Enables the Programmer to Reduce Cache Misses. Proceedings of the 14th IASTED International Conference on Parallel and Distributed Computing and Systems. ACTA Press. 2002. pp. 781-786 [BibTeX][PDF][PPT]
13. Bui Viet, K.; Desmet, L.; Dambre, J.; Beyls, K.; Van Campenhout, J.; Thienpont, H. Reconfigurable optical interconnects for parallel computer systems: design space issues. VCSELs and Optical Interconnects. SPIE. Proceedings of SPIE. Vol. 4942. 2002. pp. 236-246 [BibTeX]
14. Beyls, K.; D'Hollander, E. Reuse Distance-Based Cache Hint Selection. Proceedings of the 8th International Euro-Par Conference. Springer-Verlag. Lecture Notes in Computer Science. Vol. 2400. 2002. pp. 265-274 [BibTeX][PDF][PPT]
15. Beyls, K.; D'Hollander, E. Reuse Distance as a Metric for Cache Behavior. Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems. IASTED. 2001. pp. 617-622 [BibTeX][PS][PPT]
16. Yu, Y.; Beyls, K.; D'Hollander, E. Visualizing the Impact of the Cache on Program Execution. Proceedings of Fifth International Conference on Information Visualization. IEEE Computer Society. Information Visualization. Vol. 1 (1). 2001. pp. 336-341 [BibTeX][PDF]
17. Beyls, K.; D'Hollander, E. Cache Remapping to Improve the Performance of Tiled Algorithms. Proceedings of the 6th International Euro-Par Conference. Springer. Lecture Notes in Computer Science. 2000. pp. 998-1007 [BibTeX][PS]
18. Beyls, K.; D'Hollander, E.; Yu, Y. JPT: A Java Parallelization Tool. Proceedings of the 6th European PVM/MPI Users` Group Meeting. Springer. 1999. pp. 173-180 [BibTeX][PS]

Other publications

1. Devos, H.; Beyls, K.; Christiaens, M.; Van Campenhout, J.; Stroobandt, D. Hardware Generation from the Polyhedral Model. Proceedings of the sixth ACES Symposium. 2006. pp. 23--26 [BibTeX][Abstract][PDF][PDF]
2. Nootaert, B.; Beyls, K.; D'Hollander, E. On the calculation of Erhart polynomials in degenerate domains. . 2005. pp. 1-17 [BibTeX][PDF]
3. Buytaert, D.; Beyls, K.; De Bosschere, K. Hinting Refactorings to Reduce Object Creation In Java. Proceedings of the fifth ACES Symposium. 2005. pp. 73-76 [BibTeX][Abstract][PDF]
4. Verdoolaege, S.; Beyls, K.; Bruynooghe, M.; Catthoor, F. Experiences with Enumeration of Integer Projections of Parametric Polytopes. . KULeuven, departement computerwetenschappen. 2004. [BibTeX][Abstract][PDF]
5. Seghir, R.; Verdoolaege, S.; Beyls, K.; Loechner, V. Analytical Computation of Ehrhart Polynomials and its Application in Compile-Time Generated Cache Hints. Research Report of the Universite Louis Pasteur icps-2004-118. 2004. [BibTeX][Abstract][PDF]
6. Verdoolaege, S.; Beyls, K.; Bruynooghe, M.; Seghir, R.; Loechner, V. Analytical Computation of Ehrhart Polynomials and its Application for Embedded Systems. Technisch rapport Katholieke Universiteit Leuven, Department of Computer Science, CW376. 2004. [BibTeX][PDF]
7. Beyls, K.; D'Hollander, E. Locality-Aware Code Generation using EPIC Extensions. Program Acceleration through Application and Architecture driven Code Transformations: Symposium Proceedings. 2003. pp. 63-65 [BibTeX][Abstract]
8. Beyls, K. Automatic Design and Exploitation of Memory Hierarchies for Efficient Embedded Systems. 1st Flanders PhD Symposium: Industry-Ready Innovative Research. 2003. pp. on CD [BibTeX][Abstract][PDF]
9. Beyls, K. Faster Computing through Software-Controlled Cache Replacement. Third FTW PhD Symposium. 2002. [BibTeX][PDF][PDF]
10. Beyls, K. Cache Behavior Analysis Without Profiling. Parallel Computing: Grids and Applications. Communication & Cognition. 2002. pp. 161-174 [BibTeX][PDF][PPT]
11. Beyls, K. Cache Remapping: Faster Computing by Intelligent Data Layout. First FTW PhD Symposium. 2000. [BibTeX][PS][PS]
12. Beyls, K. The Processor-Memory Gap: Cache Remapping and Related Techniques. Parallel Architectures: Design and Exploitation, Proceedings of an international seminar. Communication and Cognition. 2000. pp. 39-48 [BibTeX][PS][PPT]
13. Beyls, K. Automatische parallellisatie van Java-programma`s. Afstudeerwerk FTW, RUG. Promotor: D'Hollander, E. 1999. [BibTeX]

Kristof Beyls, e-mail: Kristof.Beyls at elis.ugent.be