Stéphane BURIGNAT started his research carrier in the field of physics of devices successively at the INSA de Lyon, the CNRS at the Ecole Centrale de Lyon, the Université catholique de Louvain.
Rapidly, his researches focused on characterization, modeling and simulation of emerging devices such as sub-32 nm ultra-thin body and BOX SOI transistors, thin film memories, evaluation and implementation of emerging nanodevices into new functionalities in a more than Moore perspective and design of elementary circuit implementing emerging nanodevices.
Since November 2009, Stéphane BURIGNAT joined as a post-doctoral fellow the ELIS laboratory of the Gent University to work with Pr.Alexis De Vos on "Reversible Computing Electronics".
His main research activities now focus on the "physical implementation of reversible circuits".
Since November 16th 2009, he is working in the framwork of the "bilateral Danish-Belgian Micro Power" project (from 1 July 2009 to 30 June 2012).
This project is sponsored, as a strategic research project by the Commission on Strategic Growth Technologies (strategiske vaekstteknologier) of the Danish ministry for research technology and innovation.
This work is done in a close research collaboration with the informatics department (DIKU) of the Copenhagen University (Danmark) and the Computer Architecture Group of Univerity of Bremen.
See also my research pages.
Since his coming at UGent, Stéphane BURIGNAT brought several major contributions to the "physical implementation of reversible circuits" field.
He designed and successfully tested one 4-bits reversible ripple-carry adder, the so-called "Cuccaro adder" and the world-first 3-bits reversible H264/AVC video encoder. He also supervised the design and test of the world-first reversible Arithmetic Logic Unit designed by Michael Thomsen.
The 4 bits cuccaro adder gave very good results in both direction (forward-adder and backward-subtractor) either by simulations and by measurements (standard pulses and adiabatic signal).
With the 4 bits cuccaro adder, Stéphane BURIGNAT demonstrated the superiority of the use of triangular adiabatic signal compared to classical rectangular shape pulses for driving the reversible chips in both direction (forward-adder and backward-subtractor in that specific case), either by simulations and by measurements (standard pulses and adiabatic signal). The results of this study have been presented at the last MIXDES 2011 edition held on 16th-18th June 2011 at Gliwice in Poland (see also his research pages).
During his master thesis work under the supervision of Stéphane BURIGNAT, Michał Klimczak, successfully designed several Printed Circuit Boards (PCBs). These testing boards allowed to interface the reversible chips with a standard FPGA embedded on a Spantan-3E Xilinx test board proving that interfacing the reversible CMOS technology with the standard CMOS restoring technology can be done in an easy way at the small cost of 12 extra transistors for each bit of data, while keeping the reversibility (calculation direction) as a programable information. This solution has been presented at the Reversible Computation Workshop (RC 2011) held on July 4th-5th, 2011, in Gent and is published in Springer‘s Lecture Notes in Computer Science (LNCS).
During his master thesis work under the supervision of Stéphane BURIGNAT, Mariusz Olczak successfully perform an extended study on the size limit of reversible circuits in order to evaluate how large and complex a reversible circuit can be. This study showed a strong dependency of the maximun number of cascaded gates with the frequency. It also showed that sinusoidal adiabatic signals allow to push away the limits by increasing the number of possibly cascaded gate by 40 %. These results have also been presented at the Reversible Computation Workshop (RC 2011) and the article published in Springer‘s Lecture Notes in Computer Science (LNCS) as well.
The 264/AVC coder fabricated with the support of IMEC/Europractice/mini@sic in ON Semiconductor 0.35µm technology has finally been tested and gives very promissing results. The shape of the signals appear to be of best quality than even the Cuccaro adder.
This can be explained by the fact that the delays between signals are reduced in the video chip, leading to a better synchronisation of the computation flow (let precise that our reversible CMOS circuit's computation flow is asynchronous).
A third chip has been fabricated in ON Semiconductor 0.35µm technology. It is a cascade of Cuccaro Adder performing an addition followed by a subtraction performing a do-undo function such that output is equal to input. Two cascade lines of different length are embedded in this chip. The cascade length can be selected by a selection bit.
This chip allow to study the impact of the reversible circuit depth (length) on the reversible computation and its impact on performances. A model for complexity of reversible chips is in development.
Two extra circuits have been favricated in UMC 130 nm and UMC 65 nm respectively.
They are composed of one reversible full-adder circuits and one conventional full-adder circuit, both on the same chip. This will allow to compare the reversible circuits with conventional CMOS technology regarding performance and consumtion. The two chips are working properly and first results are very promissing.