Homepage of Wim Heirman
Welcome to the homepage of Wim Heirman. Since August 2003, I am working as a researcher, first as a Ph.D. student, and since July 2008 as a post-doc, at the Computer Systems Lab, which is part of the Electronics and Information Systems (ELIS) department of Ghent University in Belgium.
St. Pietersnieuwstraat 41
Fast and Accurate HPC Simulation
As of July 2010, I am part of the Flanders ExaScience Lab. This lab develops software to run on Intel-based future exascale computer systems delivering up to 1 ExaFLOPS, which is 100 times the performance of today's fastest supercomputers. The ExaScience Lab is a member of Intel's European research network – Intel Labs Europe – that consists of 21 labs employing more than 900 R&D professionals.
The PerformanceLab research group at Ghent University takes part in the ExaScience project, and is responsible for developing simulation tools that can quickly and accurately predict the performance, reliability and power requirements of future exascale HPC installations. Our simulator, Sniper, has been released as open source and can be used freely in academic research projects.
Resource allocation in a dynamic Multi-Processor System-on-Chip context
Wavelength division multiplexed on-chip optical communication
The enormous computing power of multi-processor systems and manufacturing tools now on the drawing table will require data transfer rates of over 100Terabit/s. These data rates may be needed on-chip, e.g. in multicore processors, which are expected to need total on-chip data rates of up to 100TB/s by 2015, or off-chip, e.g. in short distance data interconnects, requiring up to 100TB/s over a 10m to 100m long distance. The only viable technology for transmitting this level of information is using optical interconnects. Besides a huge data rate, optical interconnects also allow for additional flexibility through the use of wavelength division multiplexing. This additional flexibility may be employed for the realization of more intelligent interconnect systems, such as the optical network-on-chip system also investigated in this project.
WADIMOS will build a complex photonic interconnect layer incorporating multi-channel microsources, microdetectors and different advanced wavelength routing functions directly integrated with electronic driver circuits and demonstrate the application of such electro-photonic ICs in two representative applications, an on-chip optical network and a terabit optical datalink.
Reconfigurable optical interconnects
Electrical interconnection networks are being replaced by optical ones on ever shorter distances. Recent advances in inter-chip optical interconnection technologies will allow us to build tightly coupled, optically connected multiprocessor machines in the very near future. Currently, optical technologies like Myrinet and Fiber Ethernet are building blocks for large clusters, based on the message passing paradigm. The higher bandwidth, lower latency and reconfigurability of inter-chip optics (that is, directly between the digital VLSI components, avoiding slow, power-hungry and EMI-plagued electrical pins and PCBs) will allow us to build faster machines that provide a shared memory environment.
My part in this was to investigate which of the many possible optical interconnection architectures can benefit a shared memory multiprocessor, and thus finding out how the next generation of machines like the Sun Fire and SGI Altix servers may look like. Most of this task was done by simulation of the various architectures. I have set up an evaluation environment consisting of the full-system simulator Simics and the SPLASH-2 benchmarks as a workload. Since Simics only does functional simulation, I wrote a number of extension modules that model a cache-coherent, non-uniform memory access model (ccNUMA) architecture. Since these simulations take a long time, I have also looked at ways to predict performance based on network parameters, without the need for a full simulations. This is especially usefull for network designers so they can do quick design space explorations.
On July 9, 2008, I defended my Ph.D. thesis on this subject, “Reconfigurable optical interconnects in shared-memory multiprocessor systems.” The complete text, a summary and more can be found on this page.
SPLASH-2 for Solaris on SPARC on Simics
- Wim Heirman; Trevor E. Carlson; Kenzo Van Craeynest; Ibrahim Hur; Aamer Jaleel; Lieven Eeckhout Automatic SMT Threading for OpenMP Applications on the Intel Xeon Phi Co-processor. International Workshop on Runtime and Operating Systems for Supercomputers (ROSS). 2014.
- Trevor E. Carlson; Wim Heirman; Kenzo Van Craeynest; Lieven Eeckhout BarrierPoint: Sampled Simulation of Multi-threaded Applications. IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS). 2014.
- Wim Heirman; Trevor E. Carlson; Kenzo Van Craeynest; Ibrahim Hur; Aamer Jaleel; Lieven Eeckhout Undersubscribed Threading on Clustered Cache Architectures. International Symposium on High Performance Computer Architecture (HPCA). 2014.
- Trevor E. Carlson; Wim Heirman; Harish Patil; Lieven Eeckhout Efficient, Accurate and Reproducible Simulation of Multi-Threaded Workloads. Workshop on Reproducible Research Methodologies (REPRODUCE). 2014.
- Chuntao Jiang; Zhibin Yu; Hai Jin; Chengzhong Xu; Lieven Eeckhout; Wim Heirman; Trevor E. Carlson; Xiaofei Liao PCantorSim: Accelerating Parallel Architecture Simulation Through Fractal-based Sampling. ACM Transactions on Architecture and Code Optimization (TACO). Vol. 10 (4). 2013. pp. 49:1-49:24
- K. Van Craeynest; S. Akram; W. Heirman; A. Jaleel; L. Eeckhout Fairness-Aware Scheduling on Single-ISA Heterogeneous Multi-Cores. International Conference on Parallel Architectures and Compilation Techniques (PACT). 2013. pp. 177-187
- Trevor E. Carlson; Wim Heirman; Lieven Eeckhout Sampled Simulation of Multi-Threaded Applications. IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS). 2013. pp. 2-12 Best Paper Award.
- Wim Heirman; Iñigo Artundo; Christof Debaes Reconfigurable photonic networks on chip. In Ian O'Connor and Gabriela Nicolescu (Eds.), Integrated Optical Interconnect Architectures for Embedded Systems. Springer-Verlag New York, LLC. 2013. pp. 201-240
- Poona Bahrebar; Ruxandra-Marina Florea; Wim Heirman; Leon Denis; Adrian Munteanu; Dirk Stroobandt Making Communication a First-class Citizen in Multicore Partitioning. 21st Euromicro International Conference on Parallel, Distributed and Network-Based Processing. 2013.
- Francis wyffels; Karel Bruneel; Peter Bertels; Michiel D'Haene; Wim Heirman; Tim Waegeman A human-friendly way of programming robots. 5th International Workshop on Human-Friendly Robotics, Abstracts. 2012.
- Wim Heirman; Souradip Sarkar; Trevor E. Carlson; Ibrahim Hur; Lieven Eeckhout Power-Aware Multi-Core Simulation for Early Design Stage Hardware/Software Co-Optimization. International Conference on Parallel Architectures and Compilation Techniques (PACT). 2012. pp. 3-12
- Thomas J. Ashby; Pieter Ghysels; Wim Heirman; Wim Vanroose The Impact of Global Communication Latency at Extreme Scales on Krylov Methods. International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP). 2012. pp. 428-442
- Trevor E. Carlson; Wim Heirman; Lieven Eeckhout Sniper: Exploring the Level of Abstraction for Scalable and Accurate Parallel Multi-Core Simulation. Supercomputing (SC). 2011.
- Wim Heirman; Trevor E. Carlson; Shuai Che; Kevin Skadron; Lieven Eeckhout Using Cycle Stacks to Understand Scaling Bottlenecks in Multi-Threaded Workloads. International Symposium on Workload Characterization (IISWC). 2011.
- Karel Bruneel; Wim Heirman; Dirk Stroobandt Dynamic data folding with parameterizable FPGA configurations. ACM Transactions on Design Automation of Electronic Systems (ToDAES). Vol. 16 (4). 2011.
- Ma Zhe; Trevor E. Carlson; Wim Heirman; Lieven Eeckhout Evaluating application vulnerability to soft errors in multi-level cache hierarchy. 4th Workshop on Resiliency in High Performance Computing (Resilience) in Clusters, Clouds, and Grids. 2011.
- Wim Heirman; Trevor E. Carlson; Souradip Sarkar; Pieter Ghysels; Wim Vanroose; Lieven Eeckhout Using Fast and Accurate Simulation to Explore Hardware/Software Trade-offs in the Multi-Core Era. ParCo 2011. 2011.
- Robbe Vancayseele; Brahim Al Farisi; Wim Heirman; Karel Bruneel; Dirk Stroobandt RecoNoC: a reconfigurable network-on-chip. Reconfigurable Communication-centric Systems-on-Chip. 2011. p. 2
- Heirman, W.; Stroobandt, D.; Miniskar, N.R.; Wuyts, R.; Catthoor, F. PinComm: Characterizing Intra-Application Communication for the Many-Core Era. Proceedings of the 16th International Conference on Parallel and Distributed Systems (ICPADS). 2010. pp. 500-507
- Allam, A.; O'Connor, I.; Heirman, W. Performance Evaluation for Passive-Type Optical Network-on-Chip. Proceedings of the 21st IEEE International Symposium on Rapid System Prototyping. 2010.
- Debaes, C.; Artundo, I.; Heirman, W.; Van Campenhout, J.; Thienpont, H. Cycle-accurate evaluation of reconfigurable photonic networks-on-chip. Proceedings of SPIE Photonics Europe. 2010. p. 771916
- Heirman, W.; Stroobandt, D.; Miniskar, N. R.; Wuyts, R. A Communication Profiler to Optimize Embedded Resource Usage. Proceedings of the 20th ProRISC Workshop. 2009.
- Debaes, C.; Artundo, I.; Heirman, W.; Loperena, M.; Van Campenhout, J.; Thienpont, H. Architectural Study of Reconfigurable Photonic Networks-on-Chip for Multi-Core Processors. The 22nd Annual Meeting of the IEEE Photonics Society. 2009. pp. 266-267
- Artundo, I.; Loperena, M.; Debaes, C.; Thienpont, H.; Heirman, W.; Van Campenhout, J. Low-Power Reconfigurable Network Architecture for On-Chip Photonic Interconnects. Hot Interconnects 2009. 2009. pp. 163-169
- Bertels, P.; Heirman, W.; D'Hollander, E.; Stroobandt, D. Efficient Memory Management for Hardware Accelerated Java Virtual Machines. ACM Transactions on Design Automation of Electronic Systems. Vol. 14 (4). 2009.
- Bertels, P.; Heirman, W.; Stroobandt, D. Strategies for Dynamic Memory Allocation in Hybrid Architectures. Proceedings of the ACM International Conference on Computing Frontiers. 2009. pp. 217-220
- Bertels, P.; Heirman, W.; Stroobandt, D. Efficient Measurement of Data Flow Enabling Communication-Aware Parallelisation. Proceedings of the International Forum on Next-Generation Multicore / Manycore Technologies (IFMT). 2008. pp. 43-49
- Heirman, W. Reconfigurable Optical Interconnection Networks for Shared-Memory Multiprocessor Architectures. Doctoral dissertation, Faculty of Engineering, Ghent University. Promotors: Van Campenhout, J.; Stroobandt, D. 2008.
- Heirman, W.; Dambre, J.; Stroobandt, D.; Van Campenhout, J. Runtime variability in scientific parallel applications. Proceedings of the Fourth Workshop on Modeling, Benchmarking and Simulation (MoBS`08) at ISCA-35. 2008. pp. 37-46
- Artundo, I.; Heirman, W.; Debaes, C.; Dambre, J.; Van Campenhout, J.; Thienpont, H. Design of a reconfigurable optical interconnect for large-scale multiprocessor networks. Proc. of SPIE Photonics Europe. Vol. 6996. 2008. p. 69961H
- Heirman, W.; Dambre, J.; Stroobandt, D.; Van Campenhout, J. Rent’s Rule and Parallel Programs: Characterizing Network Traffic Behavior. Proceedings of the 2008 International Workshop on System Level Interconnect Prediction (SLIP`08). ACM Press. 2008. pp. 87-94
- Heirman, W.; Dambre, J.; Artundo, I.; Debaes, C.; Thienpont, H.; Stroobandt, D.; Van Campenhout, J. Predicting the performance of reconfigurable optical interconnects in distributed shared-memory systems. Photonic Network Communications. Springer Netherlands. Vol. 15 (1). 2008. pp. 25-40
- Artundo, I.; Heirman, W.; Debaes, C.; Dambre, J.; Van Campenhout, J.; Thienpont, H. Performance of large-scale reconfigurable optical interconnection networks in DSM systems. Proceedings of the IEEE/LEOS Symposium Benelux Chapter. 2007. pp. 123-126
- Heirman, W.; Artundo, I.; Dambre, J.; Debaes, C.; Pham Doan, T.; Bui Viet, K.; Thienpont, H.; Van Campenhout, J. Performance Evaluation of Large Reconfigurable Interconnects for Multiprocessor Systems. Proceedings of the International Symposium on Electrical - Electronics Engineering (ISEE 2007). 2007. pp. 145-150
- Heirman, W.; Dambre, J.; Artundo, I.; Debaes, C.; Thienpont, H.; Stroobandt, D.; Van Campenhout, J. Predicting reconfigurable interconnect performance in distributed shared-memory systems. Integration, the VLSI Journal. Elsevier B.V. Vol. 40 (4). 2007. pp. 382-393
- Heirman, W.; Dambre, J.; Van Campenhout, J. Synthetic Traffic Generation as a Tool for Dynamic Interconnect Evaluation. Proceedings of the 2007 International Workshop on System Level Interconnect Prediction (SLIP`07). ACM Press. 2007. pp. 65-72
2006 and earlier (selected)
- Artundo, I.; Manjarres, D.; Heirman, W.; Debaes, C.; Dambre, J.; Van Campenhout, J.; Thienpont, H. Reconfigurable Interconnects in DSM Systems: A Focus on Context Switch Behavior. Frontiers of High Performance Computing and Networking – ISPA 2006 Workshops. Springer Berlin / Heidelberg. Lecture Notes in Computer Science. Vol. 4331. 2006. pp. 311-321
- Artundo, I.; Desmet, L.; Heirman, W.; Debaes, C.; Dambre, J.; Van Campenhout, J.; Thienpont, H. Selective Optical Broadcast Component for Reconfigurable Multiprocessor Interconnects. IEEE Journal on Selected Topics in Quantum Electronics: Special Issue on Optical Communication. IEEE LEOS. Vol. 12 (4). 2006. pp. 828-837
- Heirman, W.; Dambre, J.; Van Campenhout, J. Congestion Modeling for Reconfigurable Inter-Processor Networks. Proceedings of the 2006 International Workshop on System Level Interconnect Prediction (SLIP`06). ACM Press. 2006. pp. 59-66
- Heirman, W.; Artundo, I.; Desmet, L.; Dambre, J.; Debaes, C.; Thienpont, H.; Van Campenhout, J. Speeding up multiprocessor machines with reconfigurable optical interconnects. Proceedings of SPIE, Optoelectronic Integrated Circuits VIII, Photonics West. SPIE. Vol. 6124. 2006. pp. 156-167
- Heirman, W.; Dambre, J.; Van Campenhout, J.; Debaes, C.; Thienpont, H. Traffic Temporal Analysis for Reconfigurable Interconnects in Shared-Memory Systems. Proceedings of the 19th IEEE International Parallel & Distributed Processing Symposium. IEEE Computer Society. 2005. p. 150
In 2009, I co-founded Dwengo, together with five other PhD students from the Computer Systems Lab. Dwengo vzw is a non-profit organisation that supports people who like to experiment with microcontrollers, and grew out of our local IEEE Student Branch's “Workshop on Electronics” (WELEK) at Ghent University. From there, we're slowly branching out into other areas such as Flemish technical high schools. We sell a PIC-based microcontroller board, the “Dwengo Board”, which is aimed at robotics and general experimentation with microcontrollers. In contrasts to our main competititors, we try to stand out with our excellent documentation and tutorials and as such fulfill our slogan to easily “get you started with microcontrollers”.
Yes, I too have a blog. No fluffy musings on my experiences of the day though, but a collection of miscellaneous writings and semi-articles on topics I keep myself occupied with, such as photography or programming. Last posts:
- Nice, France (April 2009), to the DATE conference
- South-Africa, (January 2009)
- Beijing, China (June 2008), to the ISCA conference
- Newcastle, England (April 2008), to the SLIP and NOCS conferences
- Vietnam (October 2007), on a visit to the Hanoi University of Technology and to the ISEE conference
- Scotland (August 2007)
- Austin and New York, USA (March 2007), to the SLIP conference
- Rome, Italy (Februari 2007) with the VVN, to the Frascati and Gran Sasso research labs
- Sorrento, Italy (December 2006), to the ISPA conference
- Val d'Hérence, Switzerland (September 2006) with Explorado / Te Voet
- Munich, Germany (March 2006), to the SLIP and DATE conferences
- San Jose, California (January 2006), to Photonics West
- Glasgow, Scotland (September 2005), to the ECOC conference
- San Francisco and Denver, USA (April 2005), to the SLIP and IPDPS conferences
- Munich, Germany (March 2005), to the DATE conference
- Mt. Kilimanjaro, Tanzania (February 2005)
- Val d'Anniviers, Switzerland (July 2004) with Te Voet