LCTES 2006 - Detailed Schedule

Wednesday, June 14, 2006

9:00-12:00Registration
12:00-13:15Lunch
13:15-13:30Opening
13:30-15:00Session 1: Mobile Applications
Chair: Koen De Bosschere (Ghent University, Belgium)
 
  • Feedback Linking: Optimizing Object Code Layout for Updates

       Carl von Platen (Ericsson Research, Lund, Sweden)

       Johan Eker (Ericsson Research, Lund, Sweden)

  • Minimizing Downtime in Seamless Migrations of Mobile Applications

         Kun Zhang (Georgia Institute of Technology, Atlanta, USA)

         Santosh Pande (Georgia Institute of Technology, Atlanta, USA)

  • Storing a Persistent Transactional Object Heap on Flash Memory

         Michal Spivak (Tel-Aviv University, Israel)

         Sivan Toledo (Tel-Aviv University, Israel)

15:00-15:30Break
15:30-16:30Session K: Keynote
Chair: Koen De Bosschere (Ghent University, Belgium)
 Embedded Systems in the Wild: ZebraNet Software, Hardware, and Deployment Experiences
   Margaret Martonosi (Princeton University)
16:30-16:45Break
16:45-18:15Session 2: Program analysis
Chair: Thomas Marlowe (Seton Hall University, USA)
 
  • Deriving Abstract Transfer Functions for Analyzing Embedded Software

         John Regehr (University of Utah, Salt Lake City, USA)

         Usit Duongsaa (Microsoft, USA)

  • Pluggable Abstract Domains for Analyzing Embedded Software

         Nathan Cooprider (University of Utah, Salt Lake City, USA)

         John Regehr (University of Utah, Salt Lake City, USA)

  • Field-Sensitive Value Analysis of Embedded C Programs with Union Types and Pointer Arithmetics

         Antoine Miné (École Normale Supérieure, Paris, France)

18:30-19:30Reception

Thursday, June 15, 2006

08:30-10:00Session 3: Compilation
Chair: Zhiyuan Li (Purdue University, USA)
 
  • Reducing the Cost of Conditional Transfers of Control by Using Comparison Specifications

         William Kreahling (Western Carolina University, USA)

         Stephen Hines (Florida State University, Tallahassee, USA)

         David Whalley (Florida State University, Tallahassee, USA)

         Gary Tyson (Florida State University, Tallahassee, USA)

  • Effective Thread Management on Network Processors with Compiler Analysis

         Xiaotong Zhuang (Georgia Institute of Technology, Atlanta, USA)

         Santosh Pande (Georgia Institute of Technology, Atlanta, USA)

  • In Search of Near-Optimal Optimization Phase Orderings

         Prasad Kulkarni (Florida State University, Tallahassee, USA)

         David Whalley (Florida State University, Tallahassee, USA)

         Gary Tyson (Florida State University, Tallahassee, USA)

         Jack Davidson (University of Virginia, Charlottesville, USA)

10:00-10:30Break
10:30-12:00Session 4: Real-time Techniques
Chair: Tai-Yi Huang (National Tsing Hua University, Taiwan)
 
  • An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices

         Klaus Danne (University of Paderborn, Germany)

         Marco Platzner (University of Paderborn, Germany)

  • Faster WCET Flow Analysis by Program Slicing

          Christer Sandberg (Dept. of Computer Science and Electronics, Mälardalen University, Västerås, Sweden)

          Andreas Ermedahl (Dept. of Computer Science and Electronics, Mälardalen University, Västerås, Sweden)

          Jan Gustafsson (Dept. of Computer Science and Electronics, Mälardalen University, Västerås, Sweden)

          Bjö Lisper (Dept. of Computer Science and Electronics, Mälardalen University, Västerås, Sweden)

  • Synthesizing Safe State Machines from Esterel

         Steffen Prochnow (Kiel University, Germany)

         Claus Traulsen (Kiel University, Germany)

         Reinhard von Hanxleden (Kiel University, Germany)

12:00-13:30Lunch
13:30-15:00Session P: Poster session
Chair: Mahmut Kandemir (Pennsylvania State University, USA)
 
  • Compiler Optimizations for Network Processors

       Xiaotong Zhuang (Georgia Institute of Technology, Atlanta, USA)

       Santosh Pande (Georgia Institute of Technology, Atlanta, USA)

  • A new guideline for designing low-power real-time systems

       Edward T.-H. Chu (Dept. of Computer Science, National Tsing Hua University, Hsinchu, Taiwan)

       Tai-Yi Huang (Dept. of Computer Science, National Tsing Hua University, Hsinchu, Taiwan)

  • Feasible Preemption Point Analysis for Data Cache Reference Patterns

       Harini Ramaprasad (Dept. of Computer Science, North Carolina State University, Raleigh (NC), USA)

       Frank Mueller (Dept. of Computer Science, North Carolina State University, Raleigh (NC), USA)

  • Leakage-Aware Energy-Efficient Scheduling of Periodic Real-Time Tasks in Multiprocessor Systems

        Jian-Jia Chen (Dept. of Computer Science and Information Engineering, National Taiwan University, Taipei, Taiwan)

        Tei-Wei Kuo (Dept. of Computer Science and Information Engineering, National Taiwan University, Taipei, Taiwan)

  • Automatic Region-Based Memory Management for Real-Time Embedded Systems

       Guillaume Salagnac (VERIMAG, France)

  • Using debug information in link-time analysis

       Ludo Van Put (ELIS, Ghent University, Ghent, Belgium)

       Koen De Bosschere (ELIS, Ghent University, Ghent, Belgium)

  • Energy Efficient Cross-path Scheduling for Clustered VLIW Processors

       Rahul Nagpal (Dept. of Computer Science and Automation, Indian institue of Science, Bangalore, India)

  • Abstract frequency analysis of synchronous systems

       Alexandre Chapoutot (CEA Saclay, France)

       Matthieu Martel (CEA Saclay, France)

  • A Better Global Progressive Register Allocator

       David Koes (School of Computer Science, Carnegie Mellon University, Pittsburgh (PA), USA)

       Seth Copen Goldstein (School of Computer Science, Carnegie Mellon University, Pittsburgh (PA), USA)

  • Exploitation of a Large Data Register File

       Mark Searles (Florida State University, Tallahassee, USA)

       David Whalley (Florida State University, Tallahassee, USA)

       Gary Tyson (Florida State University, Tallahassee, USA)

  • Scaling Task Graphs for Network Processors

       Martin Labrecque (Dept. of Electrical and Computer Engineering, University of Toronto, Canada)

       Gregory Steffan (Dept. of Electrical and Computer Engineering, University of Toronto, Canada)

  • A Scheme compiler for Hardware Dataflow Machines

       Xavier Saint-Mleux (Université de Montréle, Canada)

       Marc Feeley (Université de Montréle, Canada)

       Jean-Pierre David (Ecole polytechnique de Montréle, Canada)

  • Application Configurable Processors

       Chris Zimmer (Florida State University, Tallahassee, USA)

       Gary Tyson (Florida State University, Tallahassee, USA)

       David Whalley (Florida State University, Tallahassee, USA)

  • Modular Verification of TinyOS Components Using Interface Contracts

        William Archer (School of Computing, University of Utah, USA)

       John Regehr (School of Computing, University of Utah, USA)

  • HW/SW Co-Design for a Reactive Processor

       Sascha Gädtke (Dept. of Computer Science, Christian-Albrechts-Universität Kiel, Germany)

       Xin Li (Dept. of Computer Science, Christian-Albrechts-Universität Kiel, Germany)

       Marian Boldt (Dept. of Computer Science, Christian-Albrechts-Universität Kiel, Germany)

       Reinhard von Hanxleden (Dept. of Computer Science, Christian-Albrechts-Universität Kiel, Germany)

  • An OpenMP run-time performance analyzer

       Van Bui (Dept. of Computer Science, University of Houston, Houston, Texas)

       Oscar Hernandez (Dept. of Computer Science, University of Houston, Houston, Texas)

       Barbara Chapman (Dept. of Computer Science, University of Houston, Houston, Texas)

       Rick Kufrin (NCSA, University of Illinois at Urbana-Champaign, Illinois, USA)

15:00-16:00Break + poster session
16:00-17:30Session 5: Code generation
Chair: Jack Davidson (University of Virginia, USA)
 
  • Efficient Code Generation from SHIM Models

         Stephen Edwards (Columbia University, New York, USA)

         Olivier Tardieu (Columbia University, New York, USA)

  • Generating Optimized Code from SCR Specifications

         Tom Rothamel (Stony Brook University, USA)

         Yanhong A. Liu (Stony Brook University, USA)

         Constance L. Heitmeyer (Naval Research Laboratory, USA)

         Elizabeth I. Leonard (Naval Research Laboratory, USA)

  • Effective Compiler Generation by Architecture Description

         Stefan Farfeleder (TU Wien, Vienna, Austria)

         Andreas Krall (TU Wien, Vienna, Austria)

         Edwin Steiner (TU Wien, Vienna, Austria)

         Florian Brandner (TU Wien, Vienna, Austria)

Friday, June 16, 2006

08:30-10:00Session 6: Low Power Issues
Chair: David Whalley (Florida State University, USA)
 
  • Procrastination for Leakage-Aware Rate-Monotonic Scheduling on A Dynamic Voltage Scaling Processor

         Jian-Jia Chen (Department of Computer Science and Information Engineering, National Taiwan University, Taiwan)

         Tei-Wei Kuo (Department of Computer Science and Information Engineering, National Taiwan University, Taiwan)

  • Compiler-Directed Thermal Management for VLIW Functional Units

         Madhu Mutyam (International Institute of Information Technology, Hyderabad, India)

         Feihui Li (Pennsylvania State University, USA)

         Vijay Narayanan (Pennsylvania State University, USA)

         Mahmut Kandemir (Pennsylvania State University, USA)

         Mary Janie Irwin (Pennsylvania State University, USA)

  • Bypass Aware Instruction Scheduling for Register File Power Reduction

         Sanghyun Park (Seoul National University, South Korea)

         Aviral Shrivastava (University of California, Irvine, USA)

         Nikil Dutt (University of California, Irvine, USA)

         Alex Nicolau (University of California, Irvine, USA)

         Yunheung Paek (Seoul National University, South Korea)

         Eugene Earlie (Intel Corporation, USA)

10:00-10:30Break
10:30-12:00Session 7: Tools
Chair: Stephen Edwards (Columbia University, USA)
 
  • Area and Delay Estimation for FPGA Implementation of Coarse-Grained Reconfigurable Architectures

         Leipo Yan (Nanyang Technological University, Singapore)

         Thambipillai Srikanthan (Nanyang Technological University, Singapore)

         Niu Gang (Nanyang Technological University, Singapore)

  • BOTS: A Constraint-based Component System for Synthesizing Scalable Software Systems

         Raju Pandey (University of California, Davis, USA)

         Jeffrey Wu (University of California, Davis, USA)

  • Optimizing Compiler for Shared-Memory Multiple SIMD Architecture

         Weihua Zhang (Parallel Processing Institute, Fudan University, Shanghai, China)

         Xinglong Qian (Parallel Processing Institute, Fudan University, Shanghai, China)

         Ye Wang (Parallel Processing Institute, Fudan University, Shanghai, China)

         Binyu Zang (Parallel Processing Institute, Fudan University, Shanghai, China)

         Chuanqi Zhu (Parallel Processing Institute, Fudan University, Shanghai, China)